The inventive concept disclosed herein relates to delay locked loops, and more particularly, to a digital delay locked loop.
A delay locked loop (DLL) is used in a system requiring a stable clock such as a clock generator, a memory and the like and is utilized for a use such as a deskew buffer. A delay locked loop (DLL) is classified into two types, an analog delay locked loop and a digital delay locked loop. An analog delay locked loop has a superior jitter performance while having large power consumption, a long locking time and a large chip area. A digital delay locking loop increases a degree of a memory cell integration with a comparably short locking time and a small area.
However, a digital delay locked loop has a disadvantage that a static phase offset is great as compared with an analog delay locked loop. In a general digital delay locked loop, a size of detection window for locking a reference signal is designed to be greater than a resolution of fine delay line. This is because a change of process voltage temperature (PVT) should be considered. Consequently, since the maximum static phase offset of digital delay locked loop depends on a size of detection window, a general digital delay locked loop has a limit as to reduce the maximum static phase offset.